IC technology is continuously driven by a demand for higher performance chips. One limiting factor is timing delays resulting from long interconnects in 2-D structures. As a result, IC technology is progressing towards multi-tiered (3-D) IC devices (also referred to as multi-layered IC devices or stacked IC devices). In multi-tiered IC devices short vertical interconnects (also known as through-silicon vias or TSVs) replace problematic longer horizontal interconnects in 2-D structures. Two methods for creating the TSVs are via first and via last.
The via first method involves forming the TSVs in a substrate before any other fabrication of circuitry occurs. A pattern of vias is etched or drilled into a fraction of the depth of the base substrate. The vias are then filled with an insulating layer and conducting material, and circuit fabrication follows. One or more dies can then bond to the TSVs. The back side of the substrate containing the TSVs is ground down to expose the TSVs. Metallization of the exposed TSVs enables packaging of the multi-tiered structure.
In the via last method, circuitry fabrication takes place before the TSVs are formed. The circuitry contains interconnect pads that will be coupling points for the TSVs. TSVs are created by either etching or drilling into the pad through the depth of the substrate or etching or drilling from the back side of the substrate to the pad. The TSV is then filled with an insulating barrier and conducting material. The back of the substrate is metallized to enable packaging of the multi-tiered structure.
Both techniques enable building of multi-tiered structures and have specific advantages. However, each technique has undesired limitations. The via first method utilizes semiconductor fabrication processes, allowing for small vias and a resulting high packing density (ratio of surface area containing vias to the total surface area). This via first process fabricates vias having a limited aspect ratio (ratio of depth of TSV to diameter of TSV) which limits the depth of the TSV to less than the thickness of the substrate. As a result, grinding the substrate to expose the TSV reduces the substrate thickness and leads to unpredictable responses from circuitry built on the substrate. The via last method utilizes processes for forming the TSV that result in larger diameters and lower density of TSVs. The larger diameters allow the depth of the TSV to extend the entire thickness of the substrate.
It would be preferable in some situations to have TSVs of high packing density (as in the via first method) that also extend the entire depth of the substrate (as in the via last method).